Various types of semiconductor devices may be best fabricated to have one or more layers of substantially crystalline semiconductor material. For example, the highest efficiency photovoltaic solar cells presently known are III-V multi-junction cells epitaxially grown on single crystal Ge or GaAs substrates. Similarly, very high efficiency solid state lighting devices such as light emitting diodes (LEDs) and diode lasers may be fabricated from epitaxially grown nitride semiconductors such as InGaN.
Known techniques for the preparation of many crystalline semiconductor materials allow substantial defects during the epitaxial growth process which may compromise device performance. For example, there presently exists a major problem with LEDs and lasers based upon selected crystalline InGaN alloys. In particular, devices prepared from InGaN alloys have low efficiency when the alloy is selected to emit light at wavelengths between approximately 500 nm and 600 nm, corresponding to what is known as the “green gap.” One possible cause of this efficiency problem is the material quality of InGaN alloys having a suitable bandgap for emission in this wavelength region. Suitable alloys may be degraded due to a tendency toward phase separation of the InGaN prepared by conventional techniques. One possibility for avoiding this serious problem is the epitaxial growth of lattice-matched InGaN alloys in which phase separation can be suppressed. Unfortunately, no suitable substrates for the lattice matched epitaxial growth of InGaN alloys having band gaps suitable for emission in the “green gap” are known.
A similar problem exists regarding other types of semiconductor devices. A device designer may desire a crystalline semiconductor layer having specific band gap or other characteristics. It may be determined that a specific semiconductor alloy will exhibit the desired characteristics. No suitable substrate exists however, for the lattice matched growth of high quality crystalline material having the desired characteristics. Alternatively, a suitable substrate may exist but be prohibitively expensive for large scale device preparation.
For example, a significant obstacle to the widespread deployment of high efficiency, large surface area, semiconductor devices such as crystalline III-V multi junction photovoltaic cells is the extremely high cost of a suitable growth substrate. In particular, the cost of suitable quantities of single-crystal GaAs or Ge substrate can be prohibitive if the cells are prepared in quantity. Since the cost of a single crystal substrate is prohibitive, a III-V multi-junction cell may be based upon polycrystalline device layers. The inclusion of polycrystalline layers may however limit device performance.
To overcome the inefficiencies associated with polycrystalline layers, it is known in the prior art to fabricate large area, substantially crystalline, semiconductor devices beginning with a relatively inexpensive crystalline substrate which is not well lattice matched to the ultimate device layer. The fabrication of devices under these conditions typically involves several intermediate fabrication steps including the growth of several buffer layers between the substrate and the semiconductor alloy layer of interest. In particular, the need for nearly perfect lattice match between the final buffer layer and the active semiconductor layer may require a large number of buffer layers which are carefully graded to transition from the substrate lattice parameter to the lattice parameter of the active layer. This technique for obtaining an approximate lattice match between each sequentially applied layer is known as a “graded buffer layer” approach. With a graded buffer layer approach, the number of buffer layers that must be grown depends upon both the extent of lattice mismatch between the final active semiconductor layer and the substrate, and the extent of intermediate lattice mismatch which can be accepted.
Buffer layers may also be grown between the substrate and active layer to provide a chemical barrier. A chemical barrier may be needed to prevent diffusion of potentially contaminating elements from the dissimilar substrate into the semiconductor layer(s). The use of one or more buffer layers between the substrate and active semiconductor layer(s) may introduce fabrication problems. In addition, additional processing steps may increase overall device cost. Furthermore, the buffer layers themselves may introduce impurities, defects or strain issues which negatively affect device performance.
The embodiments disclosed herein are intended to overcome one or more of the limitations described above. The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings.